A digital circuit such as a microprocessor includes numerous transistors that alternate between dormant and switching states. Such digital circuits thus make abrupt current demands when large numbers of transistors switch states. But power supplies cannot react so quickly such that the voltage on the power supply's lead or interconnect to the die including the digital system may dip unacceptably. To smooth the power demands, it is conventional to load the power supply lead to the die with decoupling capacitors. The decoupling capacitors store charge that may be released during times of high power demand so as to stabilize the power supply voltage despite abrupt power demands from the powered digital circuitry.
Decoupling capacitors typically mount to the package substrate or to the circuit board and connect to the die through the power supply interconnects or leads. The interconnect distance between the decoupling capacitor and the die introduces undesirable parasitic inductance and resistance. In addition, the decoupling capacitors demand valuable package substrate or circuit board space. Integrating the decoupling capacitors into the die itself is also undesirable because the decoupling capacitors will then lower density and increase costs. The use of embedded passive capacitors within the package substrate represents another alternative. An example prior art embedded passive capacitor 105 within a substrate 100 is shown in FIG. 1A. An external power supply (not illustrated) provides a power supply voltage VDD1 to a positive terminal P of embedded capacitor 105. Embedded capacitor 105 is typically a two-terminal multiple layer ceramic capacitor (MLCC) that includes a ground terminal G. Positive terminal P also couples to a head switch 110 of a die 102. When head switch 110 is turned on, positive terminal P couples to a substrate power supply net 115 in substrate 100 that supplies power supply voltage VDD2 to die 102. Power supply voltages VDD1 and VDD2 are the same but their respective domains are separated by head switch 110. Die 102 and ground terminal G couple through substrate 100 to a common ground.
There are several problems with such a conventional arrangement. For example, charge from positive terminal P must travel roundtrip to die 102 through head switch 110, from head switch 110 back to substrate power supply net 115, and from power supply net 115 back to die 102. Such a circuitous path increases parasitic inductance and resistance. In addition, because capacitor 105 has just one positive terminal P and one ground terminal G separated by a longitudinal length for capacitor 105, a current loop 125 between these two terminals as shown conceptually in FIG. 1B is relatively large, which also increases parasitic inductance. The resulting parasitic inductance and resistance for embedded capacitor 105 lowers its quality factor Q. Such a reduced quality factor sharply limits the stabilization of substrate power supply net 115, particularly as the frequency of operation is increased for die 102.
Accordingly, there is a need in the art improved embedded capacitor architectures for power decoupling and distribution.